Texas Instruments CC2650DK Benutzerhandbuch
Functional Description
Table 13-1. General-Purpose Timer Capabilities
Prescaler Behavior
Mode
Timer Use
Count Direction
Counter Size
Prescaler Size
(1)
(Count Direction)
Timer Extension (Up),
Individual
Up or Down
16-bit
8-bit
Prescaler (Down)
One-Shot
Concatenated
Up or Down
32-bit
-
N/A
Timer Extension (Up),
Individual
Up or Down
16-bit
8-bit
Prescaler (Down)
Periodic
Concatenated
Up or Down
32-bit
-
N/A
Edge Count
Individual
Up or Down
16-bit
8-bit
Timer Extension (Both)
Edge Time
Individual
Up or Down
16-bit
8-bit
Timer Extension (Both)
PWM
Individual
Down
16-bit
8-bit
Timer Extension
(1)
The prescaler is available only when the timers are used individually.
Software configures the GPTM using the GPTM Configuration [GPT_CFG] register, the GPTM Timer A
Mode [GPT_TAMR] register, and the GPTM Timer B Mode [GPT_TBMR] register. When in one of the
concatenated modes, timer A and timer B can operate in one mode only. However, when configured in an
individual mode, timer A and timer B can be independently configured in any combination of the individual
modes.
Mode [GPT_TAMR] register, and the GPTM Timer B Mode [GPT_TBMR] register. When in one of the
concatenated modes, timer A and timer B can operate in one mode only. However, when configured in an
individual mode, timer A and timer B can be independently configured in any combination of the individual
modes.
13.3.1 GPTM Reset Conditions
After reset has been applied to the GPTM, the module is in an inactive state, and all control registers are
cleared and in their default states. Counters timer A and timer B are initialized to all 1s, along with their
corresponding load registers: the GPTM Timer A Interval Load [GPT_TAILR] register and the GPTM Timer
B Interval Load [GPT_TBILR] register. The prescale counters are initialized to 0x00:
cleared and in their default states. Counters timer A and timer B are initialized to all 1s, along with their
corresponding load registers: the GPTM Timer A Interval Load [GPT_TAILR] register and the GPTM Timer
B Interval Load [GPT_TBILR] register. The prescale counters are initialized to 0x00:
•
The GPTM Timer A Prescale [GPT_TAPR] register and the GPTM Timer B Prescale [GPT_TBPR]
register.
register.
•
The GPTM Timer A Prescale Snapshot (GPT_TAPS] register and the GPTM Timer B Prescale
Snapshot [GPT_TBPS] register.
Snapshot [GPT_TBPS] register.
•
The GPTM Timer A Prescale Value [GPT_TAPV] register and the GPTM Timer B Prescale Value
[GPT_TBPV] register.
[GPT_TBPV] register.
13.3.2 Timer Modes
This section describes the operation of the various timer modes. When using timer A and timer B in
concatenated mode, only the timer A control and status bits must be used; there is no need to use the
timer B control and status bits. The GPTM is placed into individual or split mode by writing a value of 0x4
to the GPTM Configuration [GPT_CFG] register. In the following sections, the variable n is used in bit field
and register names to imply either a timer A function or a timer B function. Throughout this section, the
time-out event in down-count mode is 0x0; in up-count mode the time-out event is the value in the GPTM
Interval Load [GPT_TnILR] and the optional GPTM Timer n Prescale [GPT_TnPR] registers.
concatenated mode, only the timer A control and status bits must be used; there is no need to use the
timer B control and status bits. The GPTM is placed into individual or split mode by writing a value of 0x4
to the GPTM Configuration [GPT_CFG] register. In the following sections, the variable n is used in bit field
and register names to imply either a timer A function or a timer B function. Throughout this section, the
time-out event in down-count mode is 0x0; in up-count mode the time-out event is the value in the GPTM
Interval Load [GPT_TnILR] and the optional GPTM Timer n Prescale [GPT_TnPR] registers.
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Timers
SWCU117A – February 2015 – Revised March 2015
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