Texas Instruments CC2650DK Benutzerhandbuch
Functional Description
Table 13-2. 16-Bit Timer With Prescaler Configurations
Prescale (8-bit value)
# of Timer Clocks (Tc)
(1)
Maximum Time
Units
00000000
1
2.7
ms
00000001
2
5.4
ms
00000010
3
8.1
ms
------------
–
–
–
11111101
254
685.8
ms
11111110
255
688.5
ms
11111111
256
691.2
ms
(1)
Tc is the clock period.
13.3.2.2 Input Edge-Count Mode
NOTE:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is ¼ of the system frequency.
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is ¼ of the system frequency.
In Edge-Count mode, the timer is configured as a 24 bit down-counter, including the optional prescaler
with the upper count value stored in the GPTM Timer n Prescale [GPT_TnPR] register and the lower bits
in the [GPT_TnR] register. In this mode, the timer is capable of capturing three types of events: rising
edge, falling edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of the [GPT_TnMR]
register must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of
the [GPT_CTL] register. During initialization in down-count mode, the [GPT_TnMATCHR] and
[GPT_TnPMR] registers are configured so that the difference between the value in the [GPT_TnILR] and
[GPT_TnPR] registers and the [GPT_TnMATCHR] and [GPT_TnPMR] registers equals the number of
edge events that must be counted. In up-count mode, the timer counts from 0x0 to the value in the
[GPT_TnMATCHR] and [GPT_TnPMR] registers.
with the upper count value stored in the GPTM Timer n Prescale [GPT_TnPR] register and the lower bits
in the [GPT_TnR] register. In this mode, the timer is capable of capturing three types of events: rising
edge, falling edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of the [GPT_TnMR]
register must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of
the [GPT_CTL] register. During initialization in down-count mode, the [GPT_TnMATCHR] and
[GPT_TnPMR] registers are configured so that the difference between the value in the [GPT_TnILR] and
[GPT_TnPR] registers and the [GPT_TnMATCHR] and [GPT_TnPMR] registers equals the number of
edge events that must be counted. In up-count mode, the timer counts from 0x0 to the value in the
[GPT_TnMATCHR] and [GPT_TnPMR] registers.
shows the values that are loaded into the
timer registers when the timer is enabled.
Table 13-3. Counter Values When the Timer is Enabled in Input Edge-Count Mode
Register
Count Down Mode
Count Up Mode
[GPT_TnR]
GPT_TnILR
0x0
[GPT_TnV]
GPT_TnILR
0x0
[GPT_TnPV]
GPT_TnPR
0x0
When software writes the TnEN bit in the GPTM Control [GPT_CTL] register, the timer is enabled for
event capture. Each input event on the CCP pin decrements or increments the counter by 1 until the event
count matches the [GPT_TnMATCHR] and the [GPT_TnPMR] registers. When the counts match, the
GPTM asserts the CnMRIS bit in the GPTM Raw Interrupt Status [GPT_RIS] register, and holds it until it
is cleared by writing the GPTM Interrupt Clear [GPT_ICR] register. If the capture mode match interrupt is
enabled in the GPTM Interrupt Mask [GPT_IMR] register, the GPTM also sets the CnMMIS bit in the
GPTM Masked Interrupt Status [GPT_MIS] register. In this mode, the GPT_TnR register holds the count
of the input events while the [GPT_TnV] and [GPT_TnPV] registers hold the free-running timer value and
the free-running prescaler value.
event capture. Each input event on the CCP pin decrements or increments the counter by 1 until the event
count matches the [GPT_TnMATCHR] and the [GPT_TnPMR] registers. When the counts match, the
GPTM asserts the CnMRIS bit in the GPTM Raw Interrupt Status [GPT_RIS] register, and holds it until it
is cleared by writing the GPTM Interrupt Clear [GPT_ICR] register. If the capture mode match interrupt is
enabled in the GPTM Interrupt Mask [GPT_IMR] register, the GPTM also sets the CnMMIS bit in the
GPTM Masked Interrupt Status [GPT_MIS] register. In this mode, the GPT_TnR register holds the count
of the input events while the [GPT_TnV] and [GPT_TnPV] registers hold the free-running timer value and
the free-running prescaler value.
In addition to generating interrupts, a
μDMA trigger can be generated. The μDMA trigger is enabled by
configuring and enabling the appropriate
μDMA channel.
After the match value is reached in down-count mode, the counter is then reloaded using the value in the
[GPT_TnILR] and [GPT_TnPR] registers, and stopped because the GPTM automatically clears the TnEN
bit in the [GPT_CTL] register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software. In up-count mode, the timer is reloaded with 0x0, and continues counting.
[GPT_TnILR] and [GPT_TnPR] registers, and stopped because the GPTM automatically clears the TnEN
bit in the [GPT_CTL] register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software. In up-count mode, the timer is reloaded with 0x0, and continues counting.
1078
Timers
SWCU117A – February 2015 – Revised March 2015
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