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Functional Description
13.3.2.1 One-Shot or Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTM Timer n Mode (GPT_TnMR) register. The timer is configured to count up or down using the
TnCDIR bit in the [GPT_TnMR] register.
GPTM Timer n Mode (GPT_TnMR) register. The timer is configured to count up or down using the
TnCDIR bit in the [GPT_TnMR] register.
When software sets the TnEN bit in the GPTM Control [GPTIMER_CTL] register, the timer begins
counting up from 0x0, or down from its preloaded value. Alternatively, if the TnWOT bit is set in the
[GPT_TnMR] register, once the TnEN bit is set, the timer waits for a trigger to begin counting (see
counting up from 0x0, or down from its preloaded value. Alternatively, if the TnWOT bit is set in the
[GPT_TnMR] register, once the TnEN bit is set, the timer waits for a trigger to begin counting (see
, Wait-for-Trigger Mode).
When the timer is counting down and reaches the time-out event (0x0), the timer reloads its start value
from the [GPT_TnILR] and [GPT_TnPR] registers on the next cycle. When the timer is counting up and
reaches the time-out event (the value in the [GPT_TnILR] and the optional [GPT_TnPR] registers), the
timer reloads with 0x0. If configured to be a one-shot timer, the timer stops counting and clears the TnEN
bit in the [GPT_CTL] register. If configured as a periodic timer, the timer starts counting again on the next
cycle. In periodic, snap-shot mode (the TnMR field is 0x2 and the TnSNAPS bit is set in the [GPT_TnMR
register]), the actual free-running value of the timer at the time-out event is loaded into the [GPT_TnR]
register. In this manner, software can determine the time elapsed from the interrupt assertion to the ISR
entry by examining the snapshot values and the current value of the free-running timer, which is stored in
the [GPT_TnV] register. Snapshot mode is not available when the timer is configured in one-shot mode.
from the [GPT_TnILR] and [GPT_TnPR] registers on the next cycle. When the timer is counting up and
reaches the time-out event (the value in the [GPT_TnILR] and the optional [GPT_TnPR] registers), the
timer reloads with 0x0. If configured to be a one-shot timer, the timer stops counting and clears the TnEN
bit in the [GPT_CTL] register. If configured as a periodic timer, the timer starts counting again on the next
cycle. In periodic, snap-shot mode (the TnMR field is 0x2 and the TnSNAPS bit is set in the [GPT_TnMR
register]), the actual free-running value of the timer at the time-out event is loaded into the [GPT_TnR]
register. In this manner, software can determine the time elapsed from the interrupt assertion to the ISR
entry by examining the snapshot values and the current value of the free-running timer, which is stored in
the [GPT_TnV] register. Snapshot mode is not available when the timer is configured in one-shot mode.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the
time-out event. The GPTM sets the TnTORIS bit in the GPTM Raw Interrupt Status (GPT_RIS) register,
and holds it until it is cleared by writing the GPTM Interrupt Clear [GPT_ICR] register. If the time-out
interrupt is enabled in the GPTM Interrupt Mask [GPT_IMR] register, the GPTM also sets the TnTOMIS bit
in the GPTM Masked Interrupt Status [GPT_MIS] register. By setting the TnMIE bit in the [GPT_TnMR]
register, an interrupt condition can also be generated when the timer value equals the value loaded into
the GPTM Timer n Match [GPT_TnMATCHR] and GPTM Timer n Prescale Match [GPT_TnPMR]
registers. This interrupt has the same status, masking, and clearing functions as the time-out interrupt, but
uses the match interrupt bits instead (for example, the raw interrupt status is monitored through the
TnMRIS bit in the GPTM Raw Interrupt Status [GPT_RIS] register). The interrupt status bits are not
updated by the hardware unless the TnMIE bit in the [GPT_TnMR] register is set, which is different than
the behavior for the time-out interrupt.
time-out event. The GPTM sets the TnTORIS bit in the GPTM Raw Interrupt Status (GPT_RIS) register,
and holds it until it is cleared by writing the GPTM Interrupt Clear [GPT_ICR] register. If the time-out
interrupt is enabled in the GPTM Interrupt Mask [GPT_IMR] register, the GPTM also sets the TnTOMIS bit
in the GPTM Masked Interrupt Status [GPT_MIS] register. By setting the TnMIE bit in the [GPT_TnMR]
register, an interrupt condition can also be generated when the timer value equals the value loaded into
the GPTM Timer n Match [GPT_TnMATCHR] and GPTM Timer n Prescale Match [GPT_TnPMR]
registers. This interrupt has the same status, masking, and clearing functions as the time-out interrupt, but
uses the match interrupt bits instead (for example, the raw interrupt status is monitored through the
TnMRIS bit in the GPTM Raw Interrupt Status [GPT_RIS] register). The interrupt status bits are not
updated by the hardware unless the TnMIE bit in the [GPT_TnMR] register is set, which is different than
the behavior for the time-out interrupt.
If software updates the [GPT_TnILR] or [GPT_TnPR] register while the counter is counting down, the
counter loads the new value on the next clock cycle and continues counting from the new value if the
TnILD bit in the [GPT_TnMR] register is clear. If the TnILD bit is set, the counter loads the new value after
the next time-out. If software updates the [GPT_TnILR] or the [GPT_TnPR] register while the counter is
counting up, the time-out event is changed on the next cycle to the new value. If software updates the
GPTM Timer n Value [GPT_TnV] register while the counter is counting up or down, the counter loads the
new value on the next clock cycle and continues counting from the new value. If software updates the
[GPT_TnMATCHR] or the [GPT_TnPMR] register while the counter is counting, the match registers reflect
the new values on the next clock cycle if the TnMRSU bit in the [GPT_TnMR] register is clear. If the
TnMRSU bit is set, the new value does not take effect until the next time-out.
counter loads the new value on the next clock cycle and continues counting from the new value if the
TnILD bit in the [GPT_TnMR] register is clear. If the TnILD bit is set, the counter loads the new value after
the next time-out. If software updates the [GPT_TnILR] or the [GPT_TnPR] register while the counter is
counting up, the time-out event is changed on the next cycle to the new value. If software updates the
GPTM Timer n Value [GPT_TnV] register while the counter is counting up or down, the counter loads the
new value on the next clock cycle and continues counting from the new value. If software updates the
[GPT_TnMATCHR] or the [GPT_TnPMR] register while the counter is counting, the match registers reflect
the new values on the next clock cycle if the TnMRSU bit in the [GPT_TnMR] register is clear. If the
TnMRSU bit is set, the new value does not take effect until the next time-out.
If the TnSTALL bit in the [GPT_CTL] register is set, the timer freezes counting while the processor is
halted by the debugger. The timer resumes counting when the processor resumes execution.
halted by the debugger. The timer resumes counting when the processor resumes execution.
shows a variety of configurations for a 16-bit free-running timer while using the prescaler. All
values assume a 24-MHz clock with Tc =41.67 ns (clock period). The prescaler can only be used when a
16- or 32-bit timer is configured in 16-bit mode.
16- or 32-bit timer is configured in 16-bit mode.
1077
SWCU117A – February 2015 – Revised March 2015
Timers
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