Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP Benutzerhandbuch
6.6
TCP2 Input Configuration Register 4 (TCPIC4)
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Registers
The TCP2 input configuration register 4 (TCPIC4) is shown in
and described in
.
TCPIC4 informs the TCP2 on the EDMA3 data flow segmentation.
Figure 37. TCP2 Input Configuration Register 4 (TCPIC4)
31
16
Reserved
R/W-0
15
13
12
8
7
6
5
0
Reserved
CRCITERPASS
Reserved
CRCLEN
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. TCP2 Input Configuration Register 4 (TCPIC4) Field Descriptions
Bit
Field
Value
Description
31-13
Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
12-8
CRCITERPASS
1-31
Number of consecutive CRC passing iterations required before decoder termination
0
1
1
1 to31
7-6
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
5-0
CRCLEN
0-32
CRC polynomial length
0
Disable CRC
1
1 to 32 = CRC polynomial length
SPRUGK1 – March 2009
TMS320C6457 Turbo-Decoder Coprocessor 2
31