Renesas rl78 User Manual
RL78/G1A
CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00
192
Jul 04, 2013
Figure 6-4. Internal Block Diagram of Channel 5 of Timer Array Unit 0
Count cloc
k
selection
TO05
PMxx
CKS050 CCS05 STS052 STS051 STS050
MD052
CIS051 CIS050 MD053
MD051 MD050
OVF
05
INTTM05
(Timer interrupt)
(Timer interrupt)
CK00
CK01
f
MCK
f
TCLK
Interrupt
controller
controller
Output
controller
Output latch
(Pxx)
Timer status
register 05 (TSR05)
register 05 (TSR05)
Overflow
Timer data register 05 (TDR05)
Timer counter register 05 (TCR05)
Timer mode register 05 (TMR05)
Channel 5
Timer controller
Mode
selection
Edge
detection
Interrupt signal from master channel
T
rigger
selection
Count cloc
k
selection
Oper
ating
cloc
k selection
CKS051
TIS01 TIS00
f
SUB
f
IL
TI05
Timer input select
register 0 (TIS0)
TIS02
Selector
Figure 6-5. Internal Block Diagram of Channel 7 of Timer Array Unit 0
TO07
PMxx
CKS070 CCS07 STS072 STS071 STS070
MD072
CIS071 CIS070 MD073
MD071 MD070
OVF
07
INTTM07
(Timer interrupt)
(Timer interrupt)
CK00
CK01
f
MCK
f
TCLK
TI07
ISC1
RxD2
Input switch
control register
(ISC)
Interrupt
controller
controller
Output
controller
Output latch
(Pxx)
Timer status
register 07 (TSR07)
register 07 (TSR07)
Overflow
Timer data register 07 (TDR07)
Timer counter register 07 (TCR07)
Timer mode register 07 (TMR07)
Timer controller
Mode
selection
Edge
detection
Interrupt signal from master channel
Channel 7
T
rigger
selection
Count cloc
k
selection
Oper
ating
cloc
k selection
Selector
CKS071