Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  6   TIMER  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

216  

Jul 04, 2013 

The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. 

Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal. 

When the noise filter is enabled, after synchronization with the operating clock (f

MCK

) for the target channel, whether the 

signal keeps the same value for two clock cycles is detected.  When the noise filter is disabled, the input signal is only 

synchronized with the operating clock (f

MCK

) for the target channel

. 

The NFEN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction. 

Reset signal generation clears this register to 00H.   

 

Note  For details, see 6.5.1 (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1), 6.5.2  

Start timing of counter and 6.7  Timer Input (TImn) Cntorol. 

 

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