Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  6   TIMER  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

228  

Jul 04, 2013 

<1>  Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. 

<2>  Timer count register mn (TCRmn) holds the initial value until start trigger generation. 

<3>  Rising edge of the TImn input is detected. 

<4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and 

count starts. 

<5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the value of 

the TCRmn register becomes FFFFH and counting stops. 

Remarks 1.  The timing is shown in Figure 6-26 indicates while the noise filter is not used.  By making the noise 

filter on-state, the edge detection becomes 2 f

MCK

 cycles (it sums up to 3 to 4 cycles) later than the 

normal cycle of TImn input.  The error per one period occurs by the asynchronous between the 

period of the TImn input and that of the count clock (f

MCK

). 

m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output 

pin (TOmn) : n = 0, 1, 3 to 7)) 

 

f

MCK

(f

TCLK

)

TSmn (write) 

TEmn 

TImn input 

<1> 

<2>

Rising edge 

Edge detection

<4>

TCRmn 

Initial value

1 

Start trigger  

detection signal 

<3>

m 

0 

FFFF

INTTMmn 

Start trigger input wait status 

<5>