Renesas rl78 User Manual

Page of 1004
 
RL78/G1A 
 
CHAPTER  6   TIMER  ARRAY  UNIT 
R01UH0305EJ0200  Rev.2.00 
 
 
248  
Jul 04, 2013 
Figure 6-46.  Example of Basic Timing of Operation as External Event Counter  
 
TSmn
TEmn
TImn
TDRmn
TCRmn
0003H
0002H
0
0000H
1
3
0
1
2
0
1
2
1
2
3
2
INTTMmn
4 events
4 events
3 events
 
 
Remarks 1.  m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output 
pin (TOmn) : n = 0, 1, 3 to 7)) 
 2.  TSmn: 
Bit n of timer channel start register m (TSm) 
 
 
TEmn: 
Bit n of timer channel enable status register m (TEm) 
 
 
TImn: 
TImn pin input signal 
 
 
TCRmn:  Timer count register mn (TCRmn) 
 
 
TDRmn:  Timer data register mn (TDRmn)