Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  6   TIMER  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

268  

Jul 04, 2013 

 

 Software 

Operation 

Hardware 

Status 

 

Power-off status 

(Clock supply is stopped and writing to each register is 

disabled.) 

Sets the TAUmEN bit of peripheral enable register 0 

(PER0) to 1.  

 

Power-on status.  Each channel stops operating. 

(Clock supply is started and writing to each register is 

enabled.) 

TAU 

default 

setting 

Sets timer clock select register m (TPSm). 

Determines clock frequencies of CKm0 to CKm3. 

 

Channel 

default 

setting 

Sets corresponding bit of noise filter enable register 1 

(NFEN1) to 0 (OFF) or 1 (ON). 

Sets timer mode register mn (TMRmn) (determines 

operation mode of channel). 

INTTMmn output delay is set to timer data register mn 

(TDRmn). 

Clears the TOEmn bit to 0 and stops operation of TOmn.

Channel stops operating. 

(Clock is supplied and some power is consumed.) 

Sets the TSmn bit to 1. 

The TSmn bit automatically returns to 0 because it is a 

trigger bit. 

TEmn = 1, and the start trigger detection (the valid edge 

of the TImn pin input is detected or the TSmn bit is set to 

1) wait status is set. 

Operation 

start 

The counter starts counting down by the next start trigger 

detection. 
• Detects the TImn pin input valid edge.  
• Sets the TSmn bit to 1 by the software. 

 

 

Value of the TDRmn register is loaded to the timer count 

register mn (TCRmn). 

During 

operation 

Set value of the TDRmn register can be changed. 

The TCRmn register can always be read. 

The TSRmn register is not used. 

The counter (TCRmn) counts down.  When the count 

value of TCRmn reaches 0000H, the INTTMmn output is 

generated, and the count operation stops until the next 

start trigger detection (the valid edge of the TImn pin input 

is detected or the TSmn bit is set to 1). 

Operation 

stop 

The TTmn bit is set to 1. 

The TTmn bit automatically returns to 0 because it is a 

trigger bit. 

TEmn = 0, and count operation stops. 

The TCRmn register holds count value and stops. 

 

TAU 

stop 

The TAUmEN bit of the PER0 register is cleared to 0.

 

Power-off status 

All circuits are initialized and SFR of each channel is 

also initialized. 

 

Remark  m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output pin 

(TOmn) : n = 0, 1, 3 to 7)) 

 

Oper

ation is 

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