Renesas rl78 User Manual
RL78/G1A
CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00
356
Jul 04, 2013
Table 11-3. A/D Conversion Time Selection (4/4)
(4) 8-bit resolution mode (ADTYP = 1) When there is A/D power supply stabilization wait time
(hardware trigger wait mode (except second and subsequent conversion in sequential conversion mode and conversion of
channel specified by scan 1, 2, and 3 in scan mode
Note 1
))
A/D Power Supply Stabilization Wait Time + Conversion Time
Selection
A/D Converter Mode Register
0 (ADM0)
AV
DD
= 1.6 to 3.6 V AV
DD
= 1.6 to 3.6 V AV
DD
= 1.8 to 3.6 V AV
DD
= 2.4 to 3.6 V AV
DD
= 2.7 to 3.6 V
FR2 FR1 FR0 LV1 LV0
Mode
Conversion
Clock (f
AD
)
Number of
A/D Power
Supply
Stabilization
Wait Clock
Number of
Conversion
Clock
A/D Power
Supply
Stabilization
Wait Time
+Conversion
Time
f
CLK
= 1 MHz
f
CLK
= 4 MHz
f
CLK
= 8 MHz f
CLK
= 16 MHz f
CLK
= 32 MHz
0 0 0
f
CLK
/32
1316/f
CLK
Setting
prohibited
41.125
μs
Note 2
0 0 1
f
CLK
/16
660/f
CLK
Setting
prohibited
41.25
μs
Note 2
20.625
μs
Note 2
0 1 0
f
CLK
/8
332/f
CLK
41.5
μs
Note 2
20.75
μs
Note 2
10.375
μs
Note 2
0 1 1
f
CLK
/6
250/f
CLK
31.25
μs
Note 2
15.625
μs
Note 2
7.8125
μs
Note 2
1 0 0
f
CLK
/5
209/f
CLK
Setting
prohibited
25.125
μs
Note 2
13.0625
μs
Note 2
6.53125
μs
Note 2
1 0 1
f
CLK
/4
168/f
CLK
42
μs
Note 2
21
μs
Note 2
10.5
μs
Note 2
5.25
μs
Note 2
1 1 0
f
CLK
/2
4 f
CLK
86/f
CLK
Setting
prohibited
21.5
μs
Note 2
10.75
μs
Note 2
5.375
μs
Note 2
2.6875
μs
Note 2
1 1 1
0 0
Normal
1
f
CLK
/1 2
f
CLK
41 f
AD
(number
of
sampling
clock:
11 f
AD
)
43/f
CLK
43
μs
Note 2
10.75
μs
Note 2
5.375
μs
Note 2
2.6875
μs
Note 2
Setting
prohibited
0 0 0
f
CLK
/32
1754/f
CLK
Setting
prohibited
54.8125
μs
0 0 1
f
CLK
/16
906/f
CLK
Setting
prohibited
56.625
μs 28.3125 μs
0 1 0
f
CLK
/8
482/f
CLK
60.25
μs
Note 2
30.125
μs 15.0625 μs
0 1 1
f
CLK
/6
376/f
CLK
47
μs
Note 2
23.5
μs 11.75
μs
1 0 0
f
CLK
/5
323/f
CLK
Setting
prohibited
40.375
μs
Note 2
20.1875
μs 10.09375 μs
1 0 1
f
CLK
/4
270/f
CLK
67.5
μs
Note 2
33.75
μs
Note 2
16.875
μs 8.4375 μs
1 1 0
f
CLK
/2
58 f
CLK
164/f
CLK
Setting
prohibited
41
μs
Note 2
20.5
μs
Note 2
10.25
μs 5.125
μs
1 1 1
0 1
Normal
2
f
CLK
/1 29
f
CLK
53 f
AD
(number
of
sampling
clock:
23 f
AD
)
82/f
CLK
82
μs
Note 2
20.5
μs
Note 2
10.25
μs
Note 2
5.125
μs Setting
prohibited
0 0 0
f
CLK
/32
2031/f
CLK
Setting
prohibited
63.46875
μs
Note 2
0 0 1
f
CLK
/16
1023/f
CLK
Setting
prohibited
63.9375
μs
Note 2
31.96875
μs
Note 2
0 1 0
f
CLK
/8
519/f
CLK
64.875
μs 32.4375 μs
Note 2
16.21875
μs
Note 2
0 1 1
f
CLK
/6
393/f
CLK
49.125
μs 24.5625 μs
Note 2
12.28125
μs
Note 2
1 0 0
f
CLK
/5
330/f
CLK
Setting
prohibited
41.25
μs
20.625
μs
Note 2
10.3125
μs
Note 2
1 0 1
f
CLK
/4
267/f
CLK
66.75
μs
Note 2
33.375
μs 16.6875 μs
Note 2
8.34375
μs
Note 2
1 1 0
f
CLK
/2
141/f
CLK
Setting
prohibited
35.25
μs
Note 2
17.625
μs 8.8125 μs
Note 2
4.40625
μs
Note 2
1 1 1
1 0 Low-
voltage 1
f
CLK
/1
15 f
CLK
63 f
AD
(number
of
sampling
clock:
33 f
AD
)
78/f
CLK
78
μs
Note 2
19.5
μs
Note 2
9.75
μs
4.875
μs
Note 2
Setting
prohibited
0 0 0
f
CLK
/32
6952/f
CLK
Setting
prohibited
217.25
μs
Note 2
0 0 1
f
CLK
/16
3480/f
CLK
Setting
prohibited
217.5
μs
Note 2
108.75
μs
Note 2
0 1 0
f
CLK
/8
1744/f
CLK
218
μs
109
μs
Note 2
54.5
μs
Note 2
0 1 1
f
CLK
/6
1310/f
CLK
163.75
μs
Note 2
81.875
μs
Note 2
40.9375
μs
Note 2
1 0 0
f
CLK
/5
1093/f
CLK
Setting
prohibited
136.625
μs
Note 2
68.3125
μs
Note 2
34.15625
μs
Note 2
1 0 1
f
CLK
/4
876/f
CLK
219
μs
109.5
μs
Note 2
54.75
μs
Note 2
27.375
μs
Note 2
1 1 0
f
CLK
/2
442/f
CLK
Setting
prohibited
110.5
μs
55.25
μs
Note 2
27.625
μs
Note 2
13.8125
μs
Note 2
1 1 1
1 1 Low-
voltage 2
f
CLK
/1
8 f
CLK
217 f
AD
(number
of
sampling
clock:
187 f
AD
)
225/f
CLK
225
μs 56.25
μs
28.125
μs
Note 2
14.0625
μs
Note 2
Setting
prohibited
(Notes, Cautions and Remark are listed on the next page.)
<R>