Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  13   SERIAL  INTERFACE  IICA 

 

SPT0

 

Stop condition trigger 

0 

Stop condition is not generated. 

1 

Stop condition is generated (termination of master device’s transfer). 

Cautions concerning set timing 
• For master reception:  

Cannot be set to 1 during transfer. 

 

Can be set to 1 only in the waiting period when the ACKE0 bit has been cleared to 0 and 

slave has been notified of final reception. 

• For master transmission:  A stop condition cannot be generated normally during the acknowledge period.  

Therefore, set it during the wait period that follows output of the ninth clock. 

• Cannot be set to 1 at the same time as start condition trigger (STT0). 
• The SPT0 bit can be set to 1 only when in master mode. 
• When the WTIM0 bit has been cleared to 0, if the SPT0 bit is set to 1 during the wait period that follows output of 

eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock.  The WTIM0 

bit should be changed from 0 to 1 during the wait period following the output of eight clocks, and the SPT0 bit should 

be set to 1 during the wait period that follows the output of the ninth clock.  

• Once STT0 is set (1), setting it again (1) before the clear condition is met is not allowed. 

Condition for clearing (SPT0 = 0) 

Condition for setting (SPT0 = 1) 

• Cleared by loss in arbitration 

• Set by instruction 

• Automatically cleared after stop condition is detected  
• Cleared by LREL0 = 1 (exit from communications) 
• When IICE0 = 0 (operation stop) 
• Reset 

 

Note  The SPT0 bit is always read as 0. 

<R> 

 

 

Remark  Bit 0 (SPT0) becomes 0 when it is read after data setting. 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013