Renesas rl78 User Manual

RL78/G1A

CHAPTER 21 VOLTAGE DETECTOR

21.3.1 Voltage detection register (LVIM)

This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well

as to check the LVD output mask status.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Figure 21-2. Format of Voltage Detection Register (LVIM)

Address: FFFA9H After reset: 00H

Note 1

R/W

Note 2

Symbol

<7>

6 5 4 3 2

<1>

<0>

LVIM LVISEN

Note 3

0 0 0 0 0

LVIOMSK

LVIF

LVISEN

Note 3

Specification of whether to enable or disable rewriting the voltage detection level

Disabling of rewriting the LVIS register (LVIOMSK = 0 (Mask of LVD output is invalid)

Enabling of rewriting the LVIS register (LVIOMSK = 1 (Mask of LVD output is valid)

<R>

LVIOMSK

Mask status flag of LVD output

Mask of LVD output is invalid

Mask of LVD output is valid

Note 4

<R>

LVIF

Voltage detection flag

Supply voltage (V

)

≥ detection voltage (V

LVD

), or when LVD is off

Supply voltage (V

) < detection voltage (V

LVD

)

<R>

Notes 1. The reset value changes depending on the reset source.

If the LVIS register is reset by LVD, it is not reset but holds the current value. In other reset, LVISEN is

cleared to 0.

2. Bits 0 and 1 are read-only.

LVISEN can only be set in the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0). Do not

change the initial value in other modes.

<R>

LVIOMSK bit is only automatically set to “1” when the interrupt & reset mode is selected (option byte

LVIMDS1, LVIMDS0 = 1, 0) and reset or interrupt by LVD is masked.

• Period during LVISEN = 1
• Waiting period from the time when LVD interrupt is generated until LVD detection voltage becomes

stable

• Waiting period from the time when the value of LVILV bit changes until LVD detection voltage becomes

stable

R01UH0305EJ0200 Rev.2.00

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Jul 04, 2013