Renesas rl78 User Manual
RL78/G1A
CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A
=
−40 to +85°C)
R01UH0305EJ0200 Rev.2.00
887
Jul 04, 2013
(9) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input)
(T
A
=
−40 to +85°C, 1.8 V ≤ EV
DD0
≤ V
DD
≤ 3.6 V, V
SS
= EV
SS0
= 0 V)
HS
Note 1
LS
Note 2
LV
Note 3
Parameter Symbol
Conditions
MIN.
MAX.
MIN.
MAX. MIN. MAX.
Unit
24 MHz < f
MCK
20/f
MCK
−
−
ns
20 MHz < f
MCK
≤ 24 MHz 16/f
MCK
−
−
ns
16 MHz < f
MCK
≤ 20 MHz 14/f
MCK
−
−
ns
8 MHz < f
MCK
≤ 16 MHz 12/f
MCK
−
−
ns
4 MHz < f
MCK
≤ 8 MHz
8/f
MCK
16/f
MCK
−
ns
2.7 V
≤ EV
DD0
≤ 3.6 V,
2.3 V
≤ V
b
≤ 2.7 V
f
MCK
≤ 4 MHz
6/f
MCK
10/f
MCK
10/f
MCK
ns
24 MHz < f
MCK
48/f
MCK
−
−
ns
20 MHz < f
MCK
≤ 24 MHz 36/f
MCK
−
−
ns
16 MHz < f
MCK
≤ 20 MHz 32/f
MCK
−
−
ns
8 MHz < f
MCK
≤ 16 MHz 26/f
MCK
−
−
ns
4 MHz < f
MCK
≤ 8 MHz
16/f
MCK
16/f
MCK
−
ns
SCKp cycle time
Note 4
t
KCY2
1.8 V
≤ EV
DD0
< 3.3 V,
1.6 V
≤ V
b
≤ 2.0 V
Note 5
f
MCK
≤ 4 MHz
10/f
MCK
10/f
MCK
10/f
MCK
ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V
t
KCY2
/2
− 18
t
KCY2
/2
− 50
t
KCY2
/2
− 50
ns
SCKp high-/low-level
width
t
KH2
,
t
KL2
1.8 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
Note 5
t
KCY2
/2
− 50
t
KCY2
/2
− 50
t
KCY2
/2
− 50
ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V
1/f
MCK
+ 20
1/f
MCK
+ 30
1/f
MCK
+ 30
ns
SIp setup time
(to SCKp
↑)
Note 6
t
SIK2
1.8 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
Note 5
1/f
MCK
+ 30
1/f
MCK
+ 30
1/f
MCK
+ 30
ns
SIp hold time
(from SCKp
↑)
Note 6
t
KSI2
1/f
MCK
+ 31
1/f
MCK
+ 31
1/f
MCK
+ 31
ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 30 pF, R
b
= 2.7 k
Ω
2/f
MCK
+ 214
2/f
MCK
+ 573
2/f
MCK
+ 573
ns
Delay time from SCKp
↓
to SOp output
Note 7
t
KSO2
1.8 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
Note 5
,
C
b
= 30 pF, R
b
= 5.5 k
Ω
2/f
MCK
+ 573
2/f
MCK
+ 573
2/f
MCK
+ 573
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
5. Use it with EV
DD0
≥ V
b
.
6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp
↓“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
7. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp
↑“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (V
DD
tolerance
(When 25- to 48-pin products)/EV
DD
tolerance (When 64-pin products)) mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For V
IH
and V
IL
, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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