Renesas rl78 User Manual
RL78/G1A
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS T
A
=
−40 to +105°C)
R01UH0305EJ0200 Rev.2.00
929
Jul 04, 2013
(4) During communication at same potential (simplified I
2
C mode)
(T
A
=
−40 to +105°C, 2.4 V ≤ EV
DD0
≤ V
DD
≤ 3.6 V, V
SS
= EV
SS0
= 0 V)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
2.7 V
≤ EV
DD0
≤ 3.6 V,
C
b
= 50 pF, R
b
= 2.7 k
Ω
400
Note 1
kHz
SCLr clock frequency
f
SCL
2.4 V
≤ EV
DD0
≤ 3.6 V,
C
b
= 100 pF, R
b
= 3 k
Ω
100
Note 1
kHz
2.7 V
≤ EV
DD0
≤ 3.6 V,
C
b
= 50 pF, R
b
= 2.7 k
Ω
1200 ns
Hold time when SCLr = “L”
t
LOW
2.4 V
≤ EV
DD0
≤ 3.6 V,
C
b
= 100 pF, R
b
= 3 k
Ω
4600 ns
2.7 V
≤ EV
DD0
≤ 3.6 V,
C
b
= 50 pF, R
b
= 2.7 k
Ω
1200 ns
Hold time when SCLr = “H”
t
HIGH
2.4 V
≤ EV
DD0
≤ 3.6 V,
C
b
= 100 pF, R
b
= 3 k
Ω
4600 ns
2.7 V
≤ EV
DD0
≤ 3.6 V,
C
b
= 50 pF, R
b
= 2.7 k
Ω
1/f
MCK
+
220
Note 2
ns
Data setup time (reception)
t
SU:DAT
2.4 V
≤ EV
DD
≤ 3.6 V,
C
b
= 100 pF, R
b
= 3 k
Ω
1/f
MCK
+
580
Note 2
ns
2.7 V
≤ EV
DD0
≤ 3.6 V,
C
b
= 50 pF, R
b
= 2.7 k
Ω
0 770 ns
Data hold time (transmission)
t
HD:DAT
2.4 V
≤ EV
DD0
≤ 3.6 V,
C
b
= 100 pF, R
b
= 3 k
Ω
0 1420 ns
Notes 1. The value must also be f
CLK
/4 or lower.
2.
Set the f
MCK
value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the normal input buffer and the N-ch open drain output (V
DD
tolerance (When 25- to 48-pin
products)/EV
DD
tolerance (When 64-pin products)) mode for the SDAr pin and the normal output mode
for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh).