Avaya 03-300430 User Manual
TDM-CLK (TDM Bus Clock)
Issue 1 June 2005
2253
See
on page 2143 for more details about the escalation
plan. There is a strong interdependency among the DS1 Interface circuit pack’s Maintenance,
Synchronization Maintenance, and TDM Bus Clock Maintenance MOs.
Synchronization Maintenance, and TDM Bus Clock Maintenance MOs.
S8700 MC
on page 2327 for a discussion of the relationship
of Tone-Clock circuits with the various reliability options.
Error Log Entries and Test to Clear Values
MASTER
DS1 Primary and
Secondary
DS1 Primary
DS1 Secondary
Local
oscillator
DS1 Primary Only
DS1 Primary
None
No External
Source
None
None
S8700 MC
SLAVE
PNC Duplication
Active EI
Standby EI
No PNC
Duplication
Active EI
None
Table 805: Synchronization - Tone Clock Roles (continued)
Tone-Clock
Role
Role
Synchronization
Facilities
Facilities
Initial External
Synchronization
Source
Synchronization
Source
Backup External
Synchronization
Source
Synchronization
Source
Internal Source
2 of 2
Table 806: TDM Bus Clock Error Log Entries
Error
Type
Type
Aux
Data
Data
Associated Test
Alarm
Level
Level
On/Off
Board
Board
1
Test to Clear Value
0 (
0
Any
Any
Any
test tone-clock location sh r 1
1 (
0
None
MIN
OFF
18 (
0
busyout tone-clock
location
WRN
OFF
release tone-clock location
130 (
None
257 (
None
WRN
OFF
513 (
)
Any
Clock Circuit Status
inquiry (#148)
MIN
2
OFF
test tone-clock location
1 of 2