Avaya 03-300430 User Manual

The Translation Update test sends the circuit-pack-level information specified by System 
Administration to the UDS1 Interface circuit pack. Translation includes the following data 
administered for a UDS1 Interface circuit pack (see output of display ds1 location): DS1 

Link Length between two DS1 endpoints, Synchronization Source Control, All Zero 
Suppression, Framing Mode, Signaling Mode, Time Slot Number of 697-Hz Tone, Time Slot 
Number of 700-Hz Tone, etc.
If a TN464F or later UDS1 circuit pack is combined with a 120A1 CSU module or the 401A T1 
sync splitter to screen an Integrated CSU module/T1 sync splitter, this test will also send the 
administration for this Integrated CSU to the circuit pack to assure the board’s translations are 
correct. The administration of the CSU module/T1 sync splitter is done using the DS1 Circuit 
Pack administration screen. Translation for the CSU module/T1 sync splitter includes the 
following data: Transmit LBO, Receive ALBO, Supply CPE Loop-Back Jack Power.

0

NO

BOARD

The test could not relate the internal ID to the port (no board). This could 
be due to incorrect translations, no board is inserted, an incorrect board 
is inserted, or an insane board is inserted.

1. Verify that the board’s translations are correct. Execute add ds1 

location to administer the UDS1 interface if it is not already 

administered.

2. If the board was already administered correctly, check the error log 

to determine whether the board is hyperactive. If so, the board was 
shut down. Reseating the board will re-initialize it.

3. If the board was found to be correctly inserted in step 1, then enter 

busyout board location.

4. Enter reset board location.
5. Enter release board location.
6. Enter test board location long.

This should re-establish the linkage between the internal ID and the port.

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