Fujitsu FR81S User Manual
CHAPTER 25: 16-BIT OUTPUT COMPARE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 16-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
4.1.2. Compare Control Register (OCS)
The bit configuration of the compare control register is shown below.
The compare control register (OCS) is used to control the output level, output enable, output level inversion
mode, compare operation enable, compare match interrupt enable, and compare match interrupt flag in
OUT0 to OUT5.
•
OCS01: Address 1250
H
(Access: Byte, Half-word, Word)
•
OCS23: Address 1258
H
(Access: Byte, Half-word, Word)
•
OCS45: Address 1260
H
(Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
BTS1
BTS0
CMOD
Reserved
OTD1
OTD0
Initial value
0
1
1
0
0
0
0
0
Attribute
R0,W0
R/W
R/W
R/W
R/W0
R/W0
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IOP1
IOP0
IOE1
IOE0
BUF1
BUF0
CST1
CST0
Initial value
0
0
0
0
1
1
0
0
Attribute
R(RM1),
W
R(RM1),
W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15] Reserved
Always write 0 to this bit.
[bit14] BTS1: Buffer transfer selection bit
BTS1
Function
0
Transfer is activated when 0 is detected (ch.1).
1
Transfer is activated when a compare clear match occurs (ch.1).
⋅
This bit is used to select the timing of data transfer from the output compare buffer register (OCCPB1)
to the output compare register (OCCP1).
⋅
When this bit is set to "0":
Data transfer is activated when the count value of "0" is detected on the 16-bit free-run timer.
⋅
When this bit is set to "1":
Data transfer is activated when a compare clear match occurs on the 16-bit free-run timer.
⋅
For ch.3 and 5, the operation is the same as ch.1.
MB91520 Series
MN705-00010-1v0-E
967