Fujitsu FR81S User Manual
CHAPTER 26: 16-BIT INPUT CAPTURE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
14
5.1. Interrupts for 16-bit Input Capture
This section explains the interrupts for 16-bit input capture
Table 5-1 shows the interrupt control bits and interrupt factor of the 16-bit input capture.
Table 5-1 Interrupt Control Bits and Interrupt Factor of 16-bit Input Capture
16-bit input capture
Even-number channel
Odd-number channel
Interrupt request
flag bit
Input capture state
control register (ICS) ICP0: bit6
Input capture state
control register (ICS) ICP1: bit7
Interrupt request
enable bit
Input capture state
control register (ICS) ICE0: bit4
Input capture state
control register (ICS) ICE1: bit5
Interrupt factor
An effective edge is detected
at the IN pin.
An effective edge is detected
at the IN pin.
With 16-bit input capture, when an effective edge is detected at a pin, the input capture state control register
(ICS) ICP1/ICP0: bit7/bit6 are set to "1". If interrupt requests are enabled (ICE1/ICE0:bit5 and bit4 of
ICS01 is 1) with this state, an interrupt request is output to the interrupt controller.
MB91520 Series
MN705-00010-1v0-E
1003