Fujitsu FR81S User Manual
CHAPTER 27: UP/DOWN COUNTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
4.3. Counter Control Register (CCR0, CCR1)
The bit configuration of the counter control register is shown below.
This register controls the up/down counter operations.
CCR0 : Address 0F74
H
(Access : Byte, Half-word)
CCR1 : Address 0F84
H
(Access : Byte, Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
M16E
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R(RM1),W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
CTUT
UCRE
RLDE
UDCC
CGSC
CGE1
CGE0
Initial value
0
0
0
0
1
0
0
0
Attribute
R0,W0
R0,W
R/W
R/W
R1,W
R/W
R/W
R/W
[bit15] M16E :
16-bit mode selection bit
This bit specifies that the up/down counter is used in 8-bit mode or in 16-bit mode.
Write value
Description
0
Uses the counter in the 8-bit mode (1 channel).
1
Uses the counter in the 16-bit mode (1 channel).
[bit14] CDCF :
Count direction change flag bit
This bit indicates that the counting direction has changed from counting down to counting up or from
counting up to counting down once or more.
counting up to counting down once or more.
When this bit is "1" and the CFIE bit is set to "1", a counting direction change interrupt request is generated.
CDCF
Read
Write
0
The counting direction is not changed.
This bit is cleared to "0".
1
The counting direction was changed once or more.
Ignored
MB91520 Series
MN705-00010-1v0-E
1018