Fujitsu FR81S User Manual

CHAPTER 27: UP/DOWN COUNTER

4. Registers

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL

Notes:

· If the counter is reset, the counting down direction is set. Therefore, if the counting up is set immediately

after the reset, this bit is changed to "1".

· If the counting direction is continuously changed in a short time, the counting direction may be returned

to the original direction and the UDF1 and UDF0 bits of counter status register (CSR) may not change.

[bit13] CFIE :

Counting direction change interrupt enable bit

Sets whether or not to generate a counting direction change interrupt request when the counting direction is
changed (CDCF=1).

Write value

Description

Disables to generate a counting direction change interrupt request.

Enables to generate a counting direction change interrupt request.

[bit12] CLKS :

Internal clock division selection bit

This bit specifies that the peripheral clock (PCLK) divided by the division ratio (set by this bit) is used as
the count clock when the timer mode is selected.

Write value

Description

Peripheral clock (PCLK) divided by 2

Peripheral clock (PCLK) divided by 8

Note:

This bit is valid only if the timer mode has been set with the CMS1 and CMS0 bits (CMS1, CMS0=00).
This bit setting is ignored if another operating mode has been selected.

[bit11, bit10] CMS1, CMS0 :

Operating mode selection bits

Select an operating mode of the up/down counter as follows.

· Timer mode

The time is counted down in synchronous with the count clock.

· Up/down count mode

Input signals entered from the two external signal input pins are counted up or down.

· Phase difference count mode

A phase difference at the two external signal input pins is counted up or down. There are two types of
phase difference count mode: the two-time multiplication mode and four-time multiplication mode. The
counting differs between the two mode types.

MB91520 Series

MN705-00010-1v0-E

1019