Fujitsu FR81S User Manual
CHAPTER 34: CLOCK SUPERVISOR
3. Register
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK SUPERVISOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
6
3.1. Clock Supervisor Control Register : CSVCR(Clock
SuperVisor Control Register)
The bit configuration of the clock supervisor control register (CSVCR) is explained.
This register sets operation mode of clock supervisor.
This register has the bit that shows the breakdown of the clock.
CSVCR : Address 056D
H
(Access: Byte)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCKS
MM
SM
RCE
MSVE
SSVE Reserved Reserved
Initial value
0
0
0
1
1
1
0
0
Attribute
R/W
R,W0
R,W0
R/W0
R/W
R/W
R0/W0
R0/W0
[bit7] SCKS (Sub Clock mode Select) : Selecting sub clock mode
Be sure to set this bit to "1" when the single clock product is used in sub clock mode.
The sub clock mode originates from divide-by-two output of the CR.
While the sub clock is being selected as a source clock (CSELR:CKS=11), writing "0" is ignored.
For dual clock product, this bit cannot be used. Be sure to write "0" to this bit.
This bit will be cleared to "0" on power-on, external reset, or simultaneous assert with NMIX. Other kind of
reset does not influence this bit.
SCKS
Description
0
Sub clock mode with CR clock as a source clock is disabled. (Initial value)
1
Sub clock mode with CR clock as a source clock is enabled.
[bit6] MM (Main clock Missing) : Main clock stop
When this bit is "1", it indicates that any problem is found in the main oscillation clock.
When this bit is "0", there are no problems in the main clock.
When the main clock is not restored, "0" write access is ignored.
This bit will be cleared to "0" on power-on or external reset. Other types of resets have no effect on this bit.
MM
Read
Write
0
Main oscillation clock stop undetected
When the main clock is restored
oscillating, this bit can be cleared
1
Main oscillation clock stop detected
No effect
Note:
Do not enable the PLL oscillation operation when this bit is "1".
MB91520 Series
MN705-00010-1v0-E
1179