Fujitsu FR81S User Manual
CHAPTER 34: CLOCK SUPERVISOR
4. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK SUPERVISOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
4.7. Checking the Reset Factor Using the Clock
Supervisor
Checking the reset factor using the clock supervisor is shown.
The method for checking whether or not the clock supervisor detected a clock problem and generated a
reset is shown below.
First, read the RSTRR register (see "4.1 Reset Source Register: RSTRR (ReSeT Result Register)" in
"CHAPTER: RESET") to check the reset factor.
If the ERST bit of the RSTRR register is "1", this indicates that either reset input from the RSTX external
pin, illegal standby mode transition detection reset, external power supply low-voltage detection, clock
supervisor reset, or simultaneous assert of RSTX and NMIX external pins was generated.
Please read the CSVCR register in this case, and confirm the MM bit. Also, read the RSTRR register (see
"4.1 Reset Source Register: RSTRR (ReSeT Result Register)" in "CHAPTER: RESET") and confirm the
reset factor.
The reset factor can be checked as follows.
Table 4-1 Reset Factor
MM
SM
Reset factor
1
0
Main clock supervisor reset
0
1
Sub clock supervisor reset
1
1
Main clock supervisor reset or Sub clock supervisor reset
[Notes]
Because the MM bit and SM bit are not cleared in conditions other than turning the power-on and the
external reset, it is necessary to confirm other reset factors reading the RSTRR register (see "4.1 Reset
Source Register: RSTRR (ReSeT Result Register)" in "CHAPTER: RESET").
MB91520 Series
MN705-00010-1v0-E
1189