Fujitsu FR81S User Manual
CHAPTER 34: CLOCK SUPERVISOR
4. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK SUPERVISOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
18
4.9. Sub Clock Mode Enabled by Setting SCKS Bit
Sub clock mode enabled by setting the SCKS bit is shown.
If the SCKS bit of the single clock product is set to "1", the device can be used in sub clock mode which
originates from divide-by-two output (50kHz) of the CR clock.
For details of procedures selecting sub clock mode, see "CHAPTER: CLOCK"
MB91520 Series
MN705-00010-1v0-E
1191