Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
[bit2] WREN (WRite ENable) : Write Enable
This bit sets whether writes to the CS area are enabled or disabled.
WREN
Writes enabled or disabled
0
Writes disabled
1
Writes enabled
The initial value for ASR0 is "0", and for not ASR is undefined.
If a write to a write-disabled area is generated from the internal bus, that access is ignored and the external
access is not performed. For an area to be written such as data area, set WREN to "1".
[bit1] LEDN (Little EnDiaN) : Little Endian
LEDN sets the byte order of the CS area.
ASR0 does not have this bit, and reading this bit always returns "0".
LEDN
Endian
0
Big endian
1
Little endian
Initial value other than ASR0 are undefined.
[bit0] CSEN (Chip Select ENable) : CS Area Enable
This bit sets whether the CS area is enabled or disabled. Operation starts according to the settings of the
ASR register, ACR register, and AWR register by setting CSEN to "1".
CSEN
CS area enabled or disabled
0
Disabled
1
Enabled
The initial value for ASR0 is "1", and for not ASR is "0".
MB91520 Series
MN705-00010-1v0-E
1208