Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
32
Access
Split
access
Output pins
Size
Address
lowermost
2 bits
A01, A00
D31 to D24
D23 to
D16
WR0X WR1X
Half-word
0n
First split
access
00
bit15 to bit8
-
○
-
Second split
access
01
bit7 to bit0
-
○
-
1n
First split
access
10
bit15 to bit8
-
○
-
Second split
access
11
bit7 to bit0
-
○
-
Word
nn
First split
access
00
bit31 to bit24
-
○
-
Second split
access
01
bit23 to bit15
-
○
-
Third split
access
10
bit15 to bit8
-
○
-
Fourth split
access
11
bit7 to bit0
-
○
-
Table 5-5 Little endian - 16 bits
Access
Split
access
Output pins
Size
Address
lowermost
2 bits
A01, A00 D31 to D24 D23 to D16 WR0X WR1X
Byte
00
-
00
bit7 to bit0
-
○
-
01
-
01
-
bit7 to bit0
-
○
10
-
10
bit7 to bit0
-
○
-
11
-
11
-
bit7 to bit0
-
○
Half-word
0n
-
00
bit7 to bit0
bit15 to bit8
○
○
1n
-
10
bit7 to bit0
bit15 to bit8
○
○
Word
nn
First split
access
00
bit7 to bit0
bit15 to bit8
○
○
Second split
access
10
bit23 to
bit16
bit31 to
bit24
○
○
MB91520 Series
MN705-00010-1v0-E
1231