Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
36
5.8. External Bus Output Signal Timing Settings
This section shows the external bus output signal timing settings.
The external bus signal output timing is determined by the following parameters. The timing parameters are
determined by the values set in the registers.
Address/Data split bus timing parameters
This section shows the timing parameters that can be configured in the address/data split bus.
Figure 5-6 Address/Data Split Bus Timing Parameters
0
A
S
C
Y
0
1
0
3
0
3
0
3
0
15
0
15
0
3
0
3
3
*
1
SYSCLK
AS
X
A00 to A21, Dxx
W
R
n
X
(
n=
0
,
1
)
RD
X
C
S
n
X
(
n
=
0
,
1
,
2
,
3
)
*1
:
The valid value output of A00 to A21 and Dxx is extended by the number of cycles specified by
RDCS during read access and by RDCS during write access.
RDCS during read access and by RDCS during write access.
A
C
S
[
1
:
0
]
R
I
D
L
[
1
:
0
]
o
r
W
R
C
V
[
1
:
0
]
CSRD[1:0]
RWT[3:0]
RDCS[1:0]
WWT[3:0]
WRCS[1:0]
CSWR[1:0]
H: Dxx is input
L: Dxx is output
L: Dxx is output
MB91520 Series
MN705-00010-1v0-E
1235