Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
6
CSIO
CSIO (Clock Synchronous Serial Interface) is a general-purpose serial data communication interface for
synchronous communication with external devices (SPI supported). It is also equipped with the FIFO for
transmission/reception (64 bytes each).
Item
Function
Data buffer
⋅
Full-duplex double buffering (when FIFO is unused)
⋅
Transmission/reception FIFO (64 bytes each) (when FIFO is used)
Transfer format
⋅
Clock synchronous (without start bit/stop bit)
⋅
Master/slave function
⋅
SPI supported (both master/slave mode supported)
Baud rate
⋅
Dedicated baud rate generator provided (comprising 15-bit reload counter, master
mode)
⋅
An external clock can be entered. (Slave operation)
Data length
Can be changed to 5 to 16, 20, 24, 32 bits
Reception error
detection
Overrun error
Interrupt request
⋅
Reception interrupt (reception completed, overrun error)
⋅
Transmission interrupt (transmission data empty, transmission bus idle, chip error
interrupt)
⋅
Transmission FIFO interrupt (when the transmission FIFO is empty)
⋅
Both transmission and reception employ extended intelligent I/O service (EI
2
OS)
and DMA function
⋅
Status interrupt (Serial timer interrupt)
Serial chip select
⋅
4-ch control (single control, round control)*
⋅
Variable setup/hold/deselect times can be set
⋅
Active level can be select for each channel
Synchronous
transmission feature
⋅
Synchronizes serial timer and is capable of automatic data transmission
periodically
Timer feature
⋅
Employs 16-bit serial timer
⋅
Dividing ratio of operating clock is selectable (1/1 to 1/256)
⋅
External trigger available
Synchronous mode Master or slave function
Pin access
Serial data output pin can be set to "1"
FIFO option
⋅
Transmission/reception FIFO equipped (transmission FIFO: 64 bytes, reception
FIFO: 64 bytes)
⋅
Transmission FIFO and reception FIFO can be selected
⋅
Transmission data can be retransmitted
⋅
Reception FIFO interrupt timing can be modified by software
⋅
FIFO reset is supported independently
DMA transfer support
Transmission: Supported
Reception: Supported
Status: Not supported
*: 4-ch control function is incorporated only for ch.4
MB91520 Series
MN705-00010-1v0-E
1319