Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

2. Features

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL



LIN-UART



Manual Mode

LIN-UART (LIN Communication Control UART) provides specific functions to support LIN bus. It is also

equipped with the FIFO for transmission/reception (64 bytes each).

Item

Function

Data buffer

⋅

Full-duplex double buffering (when FIFO is unused)

⋅

Transmission/reception FIFO (64 bytes each) (when FIFO is used)

Serial input

Execute over-sampling for three times by the bus clock and determine the reception

value by the majority of the sampling value.

Transfer mode

⋅

Asynchronous

Baud rate

⋅

Dedicated baud rate generator provided (comprising of 15-bit reload counter)

⋅

External clock input can be adjusted by the reload counter

⋅

Automatic baud rate adjustment with Sync Field reception

Data length

8 bits

Signaling system NRZ (Non Return to Zero)

Start Bit Detection Synchronize with the start bit falling edge

Reception error

detection

⋅

Framing error

⋅

Overrun error

Interrupt request

⋅

Reception interrupt

(Reception completed, framing error, overrun error)

⋅

Transmission interrupt (transmission data empty, transmission bus idle)

⋅

Status interrupt (LIN Break field detection, serial timer interrupt)

⋅

Interrupt request for ICU (LIN synch field detected: LSYN)

⋅

Transmission FIFO interrupt (when the transmission FIFO is empty)

⋅

Both transmission and reception employ extended intelligent I/O service (EI

OS)

and DMA function

Synchronous

transmission feature Synchronizes serial timer and is capable of automatic data transmission periodically

Timer feature

⋅

Employs 16-bit serial timer

⋅

Dividing ratio of operating clock is selectable (1/1 to 1/256)

⋅

External trigger available

LIN bus option

⋅

LIN protocol revision 2.1 is supported.

⋅

Master device operation

⋅

Slave device operation

⋅

LIN Break field generation (can be changed to 13 to 16 bits)

⋅

LIN Break Delimiter generation (can be changed to 1 to 4 bits)

⋅

LIN Break field detection

⋅

Detection of start/stop edges for LIN synch field connected to input capture by input

capture (See Section "CHAPTER: INPUT CAPTURE".)

FIFO option

⋅

Transmission/reception FIFO equipped (transmission FIFO: 64 bytes, reception

FIFO: 64 bytes)

⋅

Transmission FIFO and reception FIFO can be selected

⋅

Transmission data can be retransmitted

⋅

Reception FIFO interrupt timing can be modified by software

⋅

FIFO reset is supported independently

DMA transfer support

⋅

Transmission: Supported

⋅

Reception: Supported

⋅

Status: Not supported

MB91520 Series

MN705-00010-1v0-E

1320