Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

4. Registers

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

4.1.3.

FIFO Control Register 0: FCR0

FIFO control register 0 (FCR0) is used to enable/disable FIFO operation, reset FIFO, save read pointer, and

configure retransmission.



FCR0n(n=0 to 11): Address Base addr + 21

(Access: Byte, Half-word, Word)

bit

Reserved FLST

FLD

FSET

FCL2

FCL1

FE2

FE1

Initial value

R/W0

R,WX

R/W

R0,W

R/W

Attribute

[bit7] Reserved

This bit must always be written to "0".

[bit6] FLST (FIFO data LoST): FIFO retransmission data lost flag bit

This bit indicates that the retransmission data of transmission FIFO has been lost.

FLST set condition

⋅

When you write (overwrite) FIFO while the FLSTE bit of FIFO control register 1 (FCR1) is "1" and the

read pointers saved by the FSET bit matches the write pointer of transmission FIFO

FLST reset condition

⋅

FIFO reset (writing "1" to FCL)

⋅

Writing "1" to the FSET bit

If this bit is set to"1", it will overwrite the data indicated by the read pointer saved by the FSET bit. As a

result, you will not be able to configure the retransmission by the FLD bit even when an error occurs. To

execute a retransmission while this bit is set to "1", reset FIFO and write data to FIFO once again.

[bit5] FLD (FIFO pointer reLoaD bit) FIFO pointer reload bit

This bit reloads the data saved by the FSET bit at transmission FIFO to the read pointer. This bit is used for

a retransmission in case that a communication error occurs. Once the retransmission setting has completed,

this bit will be cleared to "0".

Notes:

⋅

Do not write any other than FIFO reset while this bit is set to "1" since a reload to the read pointer is in

progress.

⋅

During the FIFO enable state or while a transmission is in progress, writing "1" to this bit is prohibited.

⋅

[UART] [CSIO] [LIN-UART] This bit must be set to “1” after SCR:TIE bit and SCR:TBIE bit are set to

“0” and set SCR:TIE bit and SCR:TBIE bit to “1” after transmission FIFO is enabled.

⋅

C] This bit must be set to “1” after SMR:TIE bit is set to “0” and set SMR:TIE bit to “1” after

transmission FIFO is enabled.

[bit4] FSET (FIFO pointer SET): FIFO pointer save bit

This bit is used to save read pointer of transmission FIFO. If you save read pointer prior to communication,

you will be able to retransmit while the FLST bit is "0" in case that a communication error occurs.

If this bit is set to "1": Save the current read pointer value.

If this bit is set to "0": No effect.

Note:

Set this bit to "1" when the transmission byte count (FBYTE) is 0.

MB91520 Series

MN705-00010-1v0-E

1337