Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
42
TDIV3 TDIV2 TDIV1 TDIV0
Timer Operating Clock
Division
rate
φ
=
8MHz
φ
=
10MHz
φ
=
16MHz
φ
=
20MHz
φ
=
24MHz
φ
=
32MHz
0
0
0
0
φ
125ns
100ns
62.5ns
50ns
41.67ns 31.25ns
0
0
0
1
φ
/2
250ns
200ns
125ns
100ns 83.33ns 62.5ns
0
0
1
0
φ
/4
500ns
400ns
250ns
200ns 166.67ns 125ns
0
0
1
1
φ
/8
1µs
800ns
500ns
400ns 333.33ns 250ns
0
1
0
0
φ
/16
2µs
1.6µs
1µs
800ns 666.67ns 500ns
0
1
0
1
φ
/32
4µs
3.2µs
2µs
1.6µs
1.33µs
1µs
0
1
1
0
φ
/64
8µs
6.4µs
4µs
3.2µs
2.67µs
2µs
0
1
1
1
φ
/128
16µs
12.8µs
8µs
6.4µs
5.33µs
4µs
1
0
0
0
φ
/256
32µs
25.6µs
16µs
12.8µs 10.67µs
8µs
φ
: Bus clock
Notes:
⋅
These bits can be changed only when serial timer enable bit (TMRE) is “0”.
⋅
Any setup other than the above is prohibited.
[bit0] TMRE: Serial timer enable Bit
This bit enables/disables serial timer operations.
TMRE
Serial timer enable bit
0
Stops serial timer.
While stopped, values in the Serial Timer Register (STMR) are retained.
1
When this bit is changed from "0" to "1", the value of the Serial Timer Register
(STMR) will be initialized to "0" and serial timer will be started.
Notes:
⋅
Even if this bit is set to “1” while external trigger is enabled (TRGE="1"), serial timer will not be started
until any of external trigger edges set at the trigger selection bit (SAGSR:TRG1, 0) is detected.
⋅
When you make synchronous transmission with serial timer or transmission with external trigger, change
this bit when any of following condition is met.
⋅
Transmission is disabled (SCR:TXE="0")
⋅
Transmission bus is idling (SSR:TBI="1")
MB91520 Series
MN705-00010-1v0-E
1355