Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
86
4.4.3.
Extended Serial Control Register: ESCR
Extended communication control register (ESCR) is used to select LIN break field interrupt enable/disable,
LIN break field detection, LIN break field length, Break delimiter length settings, and stop bit length.
ESCRn(n=0 to 11) : Address Base addr + 03
H
(Access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
bit
Reserved ESBL Reserved LBIE
LBL[1:0]
DEL[1:0]
-
0
-
0
0
0
0
0
Initial value
RX,WX
R/W
RX,WX
R/W
R/W
R/W
R/W
R/W
Attribute
Bit name
Function
bit7 Reserved bit
"0" is read.
Always write "0".
bit6 ESBL:
Extended stop bit length
select bit
This bit configures the bit length of stop bit (frame end mark for
transmission data).
When SBL="0" and ESCR:ESBL="0" are set: Stop bit is set to 1 bit.
When SBL="1" and ESCR:ESBL="0" are set: Stop bit is set to 2 bits.
When SBL="0" and ESCR:ESBL="1" are set: Stop bit is set to 3 bits.
When SBL="1" and ESCR:ESBL="1" are set: Stop bit is set to 4 bits.
Notes:
⋅
When receiving, only the first bit of the stop bits will always be detected.
⋅
This bit should be set when transmission is disabled (TXE=0).
bit5 Reserved bit
Read: The value is undefined.
Write: No effect on operation.
bit4 LBIE:
LIN break field detection
interrupt enable bit
The bit to enable/disable LIN break field detection interrupt.
A reception interrupt occurs when LIN break field detection flag (LBD) is
set to "1" and interrupts are enabled (LBIE=1).
Notes:
⋅
0" is set: LIN break field detection interrupt is disabled
⋅
1" is set: LIN break field detection interrupt is enabled
bit3,
bit2
LBL[1:0]:
LIN break field length
select bits
(Functions only in the
master operation)
"00": 13-bit length
"01": 14-bit length
"10": 15-bit length
"11": 16-bit length
⋅
These bits set the length of LIN break field generation time interval (in
bits).
⋅
Before you set LBR bit in serial control register (SCR) to "1" (LIN break
field send), set this bit.
⋅
The timing of LIN break field detect is always the 11th bit at slave
operation, regardless of the set value of this bit.
Note:
⋅
This function is enabled only in the master operation (SMR:MS="0").
MB91520 Series
MN705-00010-1v0-E
1399