Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
124
4.5.3.
I
2
C Bus Status Register: IBSR
I
2
C bus status register (IBSR) indicates that repeat starts, acknowledges, data directions, arbitration lost,
stop conditions, I
2
C bus states, and bus errors have been detected.
IBSRn(n=3 to 8, 10, 11) : Address Base addr + 03
H
(Access: Byte, Half-word,
Word)
7
6
5
4
3
2
1
0
bit
FBT
RACK
RSA
TRX
AL
RSC
SPC
BB
0
0
0
0
0
0
0
0
Initial value
R,WX
R,WX
R,WX
R,WX
R,WX R(RM1),
W
R(RM1),
W
R,WX
Attribute
Bit name
Function
bit7 FBT:
First byte bit
"0" Read: Other than the first byte
"1" Read: Transmitting/receiving the first byte
This bit indicates the first byte.
FBT bit set conditions:
(1) When (repeat) starts condition detected
FBT bit clear conditions:
(1) Transmission/reception of the 2nd byte
(2) A stop condition detected
(3) I
2
C interface disable (ISMK:EN bit="0")
(4) Bus error detected (IBCR:BER bit="1")
bit6 RACK:
Acknowledge
flag bit
"0" Read: "L" Reception
"1" Read: "H" Reception
This bit indicates the acknowledges received on the first byte, in master or slave mode.
Update condition for RACK bit
(1) Acknowledgement at the first byte
(2) Acknowledgement of the data in master or slave mode
Clear condition of RACK bit (RACK bit="0")
(1) (Repeat) start condition detected
(2) I
2
C interface disable (ISMK:EN bit="0")
(3) Bus error detected (IBCR:BER bit="1")
MB91520 Series
MN705-00010-1v0-E
1437