Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

6. Operation of CSIO

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

213



Transmission/Reception operation

(1) To perform transmission and reception at the same time, enable serial data output (SMR:SOE=1) and

enable transmission/reception operation (SCR:TXE, RXE=1).

(2) When transmission data is written in TDR, SSR:TDRE=0 is set, and then serial chip select pin (SCS) will

become active at the same time of outputting the first bit and transmission/reception will be started after

the setup time is passed for the serial chip select pin. When transmission/reception is started, the

transmission data is output in synchronization with the rising edge of serial clock (SCK) output. Half a

cycle before a falling edge of the first serial clock (SCK), SSR:TDRE=1 is set, and when transmission

interrupt is enabled (SCR:TIE=1), a transmission interrupt request is output. At this time, the transmission

data of the second byte can be written.

(3) The reception data will be sampled at a falling edge of the serial clock output (SCK). Receiving the last

bit of receiving data sets SSR:RDRF=1 and when the reception interrupt is enabled (SCR:RIE=1), a

reception interrupt request will be generated. At this time, the receive data (RDR) can be read. Reading

the received data (RDR) clears SSR:RDRF to "0".

(4) After the number of data set in the TBYTE is completed for transmission/reception,

transmission/reception operation will be terminated.

(5) After hold time for the serial chip select pin is lapsed after the transmission/reception operation, the serial

chip select pin (SCS) will become inactive. However, if serial chip select active level

(SCSCR:SCAM="1") is held at this time, the serial chip select pin (SCS) will remain active.



Continuous Data Transmission or Reception Wait Operation

(1) When a setup other than (ESCR.WT1, ESCR.WT0)= (0, 0) is used for continuous data transmission or

reception, a wait will be inserted between frames.

■ ESCR.WT1=0, ESCR.WT0=1(for master)

SCK

1Byte

2Byte

1bit

■ ESCR.WT1=1, ESCR.WT0=0(for master)

SCK

1Byte

2Byte

2bit

■ ESCR.WT1=1, ESCR.WT0=1(for master)

SCK

1Byte

2Byte

3bit

TDRE

MB91520 Series

MN705-00010-1v0-E

1526