Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
258
While the overrun error flag is being set (SSR:ORE=1), the operation enable bit of the reception FIFO is
cleared (FCR0:FE1=0 or FCR0:FE2=0).
As for the timing of setting the overrun error flag bit (SSR:ORE), the timing is similar to those described in
"7.1.2 Reception Interrupts and Flag Setting Timing" in manual mode. See Figure-7.1.
LIN Bus Error Detection Interrupt and Flag Setting Timing
The LIN bus error is detected by the self-check done on the side where a header/response is transmitted in
assist mode (LAMCR:LAMEN=1). The LIN bus error cannot be detected on the side where
header/response is received.
Figure 7-8 shows the LIN bus error detection object.
Figure 7-8 LIN bus error detection object
SIN
SOUT
MPU
(header/response transmission node)
Transceiver
Transmission data
Reception data
(Self-check)
LIN bus error
Detection object
Transceiver
SIN
SOUT
MPU
(header/response reception node)
Reception data
LIN bus error
No Detection object
: LIN bus error object route
: LIN Bus error off the subject route
: LIN Bus error off the subject route
The range of detection of the LIN bus error is a start bit and byte data of LIN Break and Sync Field/ID
Field/Data Field/Check Sum Field. The stop bit is outside the detection range of the LIN bus error. When
the stop bit is detected as "L" level, the framing error is detected (SSR:FRE=1).
Moreover, when the LIN bus error is detected, transmission of the header and the response is stopped in the
assist mode.
Even if the LIN bus error occurs when the ID Field transmission is completed, LIN automatic header
completion flag (LAMSR:LAHC=1) is set.
LIN bus error detection interrupt and flag setting timing on master side
On master side (SCR:MS=0), the LIN bus error is detected when a
header/response is transmitted.
The LIN bus error is detected and the flag is set (LAMESR:LBSER=1) if abnormality is detected as a result
of the comparison between transmission LIN Break length and reception LIN Break length or between the
transmitted data and the received data. When this interrupt is set to be enabled (LAMIER:LBSERIE=1), the
reception interrupt will occur.
LIN bus error detection interrupt and flag setting timing on slave side
On slave side (SCR:MS=1), the LIN bus error is detected when the response is transmitted.
The LIN bus error is detected and the flag is set (LAMESR:LBSER=1) if abnormality is detected as a result
of the comparison between the transmitted data and the received data. When this interrupt is set to be
enabled (LAMIER:LBSERIE=1), the reception interrupt will occur.
MB91520 Series
MN705-00010-1v0-E
1571