Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
293
7.5.2. Assist Mode
The assist mode has the function the LIN automatic header transmission/reception, and the following
generation and check.
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Parity generation and check on ID Field
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Generation and check on checksum
Master operation
Automatic header transmission setting
To transmit the automatic header in the assist mode, please set the SCR:LBR bit (LIN Break Field setting
bit) to "1" after initial setting. "LIN Break Field - Sync Field - ID Field" is automatically transmitted by
setting the SCR:LBR bit to "1". The transmission setting is shown as follows.
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Please set the SCR:MS bit (master/slave function select bit) to "0" to operate as the master.
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Please set the LAMCR:LAMEN bit (LIN assist mode processing enable bit) to "1".
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Please set the ID Field value before the LIN assist mode begins.
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Please set the LAMCR:LIDEN bit (LIN ID register enable bit) to "1" when you use LIN assist mode
transmission ID register (LAMTID).
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Please set the LAMCR:LIDEN bit to "0" when you use data transmission register (TDR).
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Please set the ID Field data to LAMTID (LIN assist mode transmission ID register) when you set the
LAMCR:LIDEN bit to "1".
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Please set selection of the LIN break field length (ESCR:LBL2, LBL1, LBL0) and selection of the LIN
Break delimiter length (ESCR:DEL1, DEL0).
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Please set the selection of the stop bit length (SMR:SBL and ESCR:ESBL).
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LIN Break Field transmitted on the master side is detected also on the master side. The SSR:LBD bit is
set in "1" when detected. At this time, if ESCR:LBIE is set to "1", the status interrupt is generated. Please
set ESCR:LBIE to "0" and change the interrupt to the prohibition setting for the LIN assist mode.
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The Sync Field value transmitted on the master side is detected also on the master side. The SACSR:SFD
bit is set in "1" when detected. At this time, if the SACSR:SFDE bit is set to "1", the interrupt is
generated. Please set SACSR:SFDE to "0" for the LIN assist mode and prohibit interrupting.
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Please set transmission operation enable bit (SCR:TXE) to "1" (transmission enable).
From LIN Break Field to ID Field transmission
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Please set LIN Break Field setting bit (SCR:LBR) to "1" (LIN Break Field generation).
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LIN Break Field set with ESCR:LBL2 to LBL0 is transmitted.
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Please write the ID Field data in data transmission register (TDR) when you do not use LIN assist mode
transmission ID register (LAMTID).
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LIN Break Field that the master transmitted is reception on the master side, and the bus error is checked.
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After LIN Break Field is transmitted, the LIN Break Field delimiter set with ESCR:DEL1 and DEL0 is
transmitted.
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After the LIN Break Field delimiter is transmitted, Sync Field (0x55 fixation value) is transmitted.
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Sync Field that the master transmitted is reception on the master side, and the bus error is checked.
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After Sync Field is transmitted, the set ID Field value is transmitted. When the LAMCR:LIDEN bit is
"0", the value set to TDR is transmitted as ID FIeld value. When the LAMCR:LIDEN bit is "1", the
value set to LAMTID is transmitted as ID FIeld value.
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The LIN assist mode does the parity arithmetic operations of ID Field automatically.
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When the first bit of ID Field is transmitted, SSR:TDRE (the transmission data empty) bit is set to "1".
At this time, if transmission interrupt enable (SCR:TIE=1) is done, the transmission interrupt is
generated.
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When transmission interrupt (TDRE) is generated, the transmission data can be written in transmission
data register (TDR).
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ID Field is eight bits in the data length, and it is output with LSB first. The LIN parity in ID Field is
operated automatically.
MB91520 Series
MN705-00010-1v0-E
1606