Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
295
DATA Field transmission/reception
Whether DATA Field is transmitted or received to the slave device is selected.
(When DATA Field is transmitted)
⋅
When LIN assist mode transmission register (LAMTID) is not used, SSR:TDRE is set to "1" if the first
bit of ID Field is transmitted. At this time, DATA Field can be written.
⋅
When LIN assist mode transmission register (LAMTID) is used, DATA Field can be written after LIN
Break Field setting bit (SCR:LBR) is set to "1".
⋅
Please set the transmission enable (SCR:TXE=1) from the setting of LIN Break Field setting bit
(SCR:LBR) to "1" to starting of the response transmission.
⋅
The LIN assist mode does the checksum arithmetic operations automatically. The arithmetic operations
of checksum can select the arithmetic operations method by LIN checksum type selection bit
(LAMCR:LCSTYP).
⋅
When the transmission of checksum is completed, the transmission bus idle flag (SSR:TBI) is set. At this
time, when the transmission bus idle interrupt enable bit is set (SCR:TBIE="1"), the interrupt is
generated.
⋅
After the response transmission is completed (LAMSR:LCSC=1), transmission prohibition setting
(SCR:TXE=0) is done.
Notes:
⋅
The response transmission data (Data Field and checksum) when the assist mode operates cannot be
stored in the RDR register.
⋅
Please write data in FIFO after setting LIN Break Field setting bit (SCR:LBR) to "1" (LIN Break Field
generation bit) when you use FIFO.
⋅
Please do the dummy writing (the writing value is "don't care") to the TDR register to operate checksum
automatically and to transmit when you set the LIN data length to 0 byte length
(LAMCR:LDL3-0="0000") in the response transmission. The TDR setting value at this time doesn't
influence checksum.
⋅
The checksum value becomes the following when the LIN data length is set by 0 byte length
(LAMCR:LDL3-0="0000").
⋅
When the standard checksum is set (LAMCR:LCSTYP=0), the checksum value becomes 0xFF.
⋅
When the expanded checksum is set (LAMCR:LCSTYP=1), the checksum value becomes reversing
ID Field.
Figure 7-42 From ID Field transmission to DATA Field transmission (FIFO unused when ID
register is used)
SSR : TDRE
Sync Field
DATA Field write
ID Field
Data Field
LAMCR : LAMEN
LAMCR : LIDEN
H : LIN assist mode processing enable
H : LIN ID register use enable
LAMTID : LID5-0
LIN ID value setting
TDR
Data 1
Data 2
Data N
checksum
Data 1
Data N
LIN bus
6 7 SP ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3
0 1 2 3 4 5 6
SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7
SP
7
ST
Data (N-1）
LAMSR : LCSC
：Don’t care
LAMSR : LAHC
MB91520 Series
MN705-00010-1v0-E
1608