Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

8. Operation of I2C

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

352

Figure 8-25 Master Transmission Interrupt (11)-when FIFO is Disabled

(SSR:DMA="1", IBCR:WSEL="1", IBSR:RSA="0", ACK Response)

S Slave Address W ACK Data ACK Data ACK Data ACK P or Sr

□ □ □ □ ▲

① ② ② ③

S: Start condition

W: Data direction bit (Write direction)

P: Stop condition

Sr: Repeated start condition



: Interrupt because of CNDE = "1"



: Interrupt by TBIE= "1"

(1) An interrupt generated by slave address transmission + direction bit transmission+

acknowledgment reception

- the transmission data is written to the TDR register

(2) An interrupt generated by 1 byte transmission

- the transmission data is written to the TDR register

(3) An interrupt generated by 1 byte transmission

- Set MSS = "0" or MSS = "1" and SCC = "1"

*: The TDRE bit is "1" upon the generation of the interrupt flag (INT)

Figure 8-26 Master Transmission Interrupt (12)-when FIFO is Disabled

(SSR:DMA="0", IBCR:WSEL="1", IBSR:RSA="0", NACK Response)

S Slave Address W ACK Data ACK Data ACK Data NACK P or Sr

□ □ □ □ △▲