Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
365
8.4.1. Detection of Slave Address Matching
When the (repeated) start condition is detected, the 7 bits of the next data are received as the address. If the
bit is set to "1" in the ISMK register, it is compared with each bit of the ISBA register and the received
address. If they match, an ACK signal is output.
Table 8-9 Operations Immediately After Acknowledgment to Slave Address
Trans-
mission
FIFO
opera-
tion
Recep-
tion
FIFO
opera-
tion
Trans-
missio
n FIFO
status
Receptio
n FIFO
status
Data
direction
bit
(R/W)
Operation immediately after acknowledgement
Acknowledge is ACK Acknowledge is NACK
Disabled Disabled
-
-
0
If the SSR:TDRE bit is "1", the
IBCR:INT bit is set to "1" and
waited. If the SSR:TDRE bit is
"0", the IBCR:INT bit is held to
"0" and not waited.
The IBCR:INT bit is held
to "0" and not waited.
1
Disabled Enabled
-
Without
data
0
The IBCR:INT bit is held to
"0" and not waited.
The IBCR:INT bit is held
to "0" and not waited.
With data
The IBCR:INT bit is set to "1"
and waited.
-
1
If the SSR:TDRE bit is "1", the
IBCR:INT bit is set to "1" and
waited. If the SSR:TDRE bit is
"0", the IBCR:INT bit is held to
"0" and not waited.
Enabled Disabled
-
-
0
If the SSR:TDRE bit is "1", the
IBCR:INT bit is set to "1" and
waited. If the SSR:TDRE bit is
"0", the IBCR:INT bit is held to
"0" and not waited.
The IBCR:INT bit is held
to "0" and not waited.
1
Enabled Enabled
-
Without
data
0
The IBCR:INT bit is held to
"0" and not waited.
The IBCR:INT bit is held
to "0" and not waited.
With data
The IBCR:INT bit is set to "1"
and waited.
-
1
If the SSR:TDRE bit is "1", the
IBCR:INT bit is set to "1" and
waited. If the SSR:TDRE bit is
"0", the IBCR:INT bit is held to
"0" and not waited.
MB91520 Series
MN705-00010-1v0-E
1678