Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
4.1.4. List of Message Handler Register
This section shows the list of message handler register
Table 4-3 List of Message Handler Register
Address
Registers
Note
+0
+1
+2
+3
Base-addr + 80
H
CAN transmission request register 2
(TREQR2)
CAN transmission request register 1
(TREQR1)
INTR1, 2:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
TxRqst[32:25]
TxRqst[24:17]
TxRqst[16:9]
TxRqst[8:1]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 84
H
CAN transmission request register 4
(TREQR4)
CAN transmission request register 3
(TREQR3)
INTR3, 4:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
TxRqst[64:57]
TxRqst[56:49]
TxRqst[48:41]
TxRqst[40:33]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 88
H
Base-addr + 8C
H
Reservation area for supporting 128 message buffers
(See CAN transmission request registers (TREQR1 to TREQR4))
TREQ5 to TREQ8: 128 message buffers are supported
Base-addr + 90
H
CAN new data register 2
(NEWDT2)
CAN new data register 1
(NEWDT1)
NEWDT1, 2:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
NewDat[32:25] NewDat[24:17] NewData[16:9] NewData[8:1]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 94
H
CAN new data register 4
(NEWDT4)
CAN new data register 3
(NEWDT3)
NEWDT3, 4:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
NewDat[64:57] NewDat[56:49] NewData[48:41] NewData[40:33]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 98
H
Base-addr + 9C
H
Reservation area for supporting 128 message buffers
(See CAN data update registers (NEWDT1, NEWDT2))
NEWDT5 to NEWDT8: 128 message buffers are supported
MB91520 Series
MN705-00010-1v0-E
1706