Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
14
Address
Registers
Note
+0
+1
+2
+3
Base-addr + A0
H
CAN interrupt pending register 2
(INTPND2)
CAN interrupt pending register 1
(INTPND1)
INTPND1, 2:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
IntPnd[32:25]
IntPnd[24:17]
IntPnd[16:9]
IntPnd[8:1]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + A0
H
CAN interrupt pending register 4
(INTPND4)
CAN interrupt pending register 3
(INTPND3)
INTPND3, 4:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
IntPnd[64:57]
IntPnd[56:49]
IntPnd[48:41]
IntPnd[40:33]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + A8
H
Base-addr + AC
H
Reservation area for supporting 128 message buffers
(See CAN interrupt pending registers (INTPND1, INTPND2))
INTPND5 to INTPND8: 128 message buffers are supported
Base-addr + B0
H
CAN message valid register 2
(MSGVAL2)
CAN message valid register 1
(MSGVAL1)
MSGVAL1, 2:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MsgVal[32:25] MsgVal[24:17]
MsgVal[16:9]
MsgVal[8:1]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + B0
H
CAN message valid register 4
(MSGVAL4)
CAN message valid register 3
(MSGVAL3)
MSGVAL3, 4:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MsgVal[64:57] MsgVal[56:49] MsgVal[48:41] MsgVal[40:33]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + B8
H
Base-addr + BC
H
Reservation area for supporting 128 message buffers
(See CAN message valid registers (MSGVAL1, MSGVAL2))
MSGVAL3 to MSGVAL8: 128 message buffers are supported
MB91520 Series
MN705-00010-1v0-E
1707