Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
23
4.2.4. CAN Bit Timing Register : BTR
The bit configuration of the CAN bit timing register is shown.
Sets the prescaler and bit timing.
CAN Bit Timing Register (upper byte): Address Base + 06
H
(Access: Byte,
Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
TSeg2
TSeg1
Initial value
0
0
1
0
0
0
1
1
Attribute R0,W0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN Bit Timing Register (lower byte): Address Base + 07
H
(Access: Byte,
Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SJW
BRP
Initial value
0
0
0
0
0
0
0
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15] : Reserved bit
The read value is always "0". When writing to this bit, set "0".
[bit14 to bit12]: Time segment 2 setting bits
Valid setting values are 0 to 7. TSeg2+1 bit value is time segment 2.
Time segment 2 corresponds to the phase buffer segment (PHASE_SEG2) based on the CAN specification.
[bit11 to bit8]: Time segment 1 setting bits
Valid setting values are 1 to 15. 0 cannot be set. TSeg1+1 bit value is time segment 1.
Time segment 1 corresponds to the propagation segment (PROP_SEG) and phase buffer segment 1
(PHASE_SEG1) based on the CAN specification.
[bit7, bit6]: Resynchronization jump width setting bits
Valid setting values are 0 to 3. The SJW+1 bit value is the resynchronization jump width.
[bit5 to bit0]: Baud rate prescaler setting bits
Valid setting values are 0 to 63. The BRP+1 bit value is the baud rate prescaler.
Divides frequency for system clock (fsys) and determines the basic unit time (tq) of the CAN controller.
Note:
When "1" is set to the CCE and Init bits of the CAN control register (CTRLR), set the CAN bit timing
register (BTR) and the CAN prescaler extension register (BRPER).
MB91520 Series
MN705-00010-1v0-E
1716