Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
4.3.2. IFx Command Mask Register (IFxCMSK)
The bit configuration of the IFx command mask register is shown.
This register sets which data to be updated by controlling the direction of transfer between the message
interface register and message RAM. The register becomes invalid in the test basic mode.
IFx Command Mask Register (upper byte): Address Base + 12
H
& Base + 42
H
(Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
IFx Command Mask Register (lower byte): Address Base + 13
H
& Base + 43
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WR/RD
Mask
Arb
Control
CIP
TxRqst/
NewDat
Data A
Data B
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit8] : Reserved bit
The read value is always "0". When writing to these bits, set "0".
[bit7] WR/RD : Write/read control bit
WR/RD
Function
0
Indicates reading data from message RAM. Reading data from message RAM will be
executed by writing data to the IFx command request register (IFxCREQ). Data read
from message RAM depends on the settings of Mask, Arb, Control, CIP,
TxRqst/NewDat, Data A, and Data B bits.
[Initial value]
1
Indicates writing data to message RAM. Writing data to message RAM will be executed
by writing data to the IFx command request register (IFxCREQ). Data written to
message RAM depends on the settings of Mask, Arb, Control, CIP, TxRqst/NewDat,
Data A, and Data B bits.
Note:
Data in message RAM is undefined after reset. Reading data from message RAM is disabled while data in
message RAM is undefined.
Bit6 to bit0 of the IFx command mask register (IFxCMSK) has different meanings depending on the
settings of transfer direction (WR/RD bit).
MB91520 Series
MN705-00010-1v0-E
1724