Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
4.3.3. IFx Mask Registers 1, 2 : IFxMSK1, IFxMSK2
The bit configuration of the IFx mask registers 1, 2 is shown.
They are used to write/read message object mask data of message RAM. In the test basic mode, the
configured mask data becomes invalid.
See "4.4 Message Object" for the functions of each bit.
IFx Mask Register 2 (upper byte): Address Base + 14
H
& Base + 44
H
(Access:
Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MXtd
MDir
Reserved
Mask28 to Mask24
Initial value
1
1
1
1
1
1
1
1
Attribute
R/W
R/W
R1,W1
R/W
R/W
R/W
R/W
R/W
IFx Mask Register 2 (lower byte): Address Base + 15
H
& Base + 45
H
(Access:
Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Mask23 to Mask16
Initial value
1
1
1
1
1
1
1
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IFx Mask Register 1 (upper byte): Address Base + 16
H
& Base + 46
H
(Access:
Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Mask15 to Mask8
Initial value
1
1
1
1
1
1
1
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IFx Mask Register 1 (lower byte): Address Base + 17
H
& Base + 47
H
(Access:
Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Mask7 to Mask0
Initial value
1
1
1
1
1
1
1
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
See "4.4 Message Object" for explanation of bits.
For the reserved bit (bit13 of IFx mask register 2), "1" is read out. When writing to this bit, set "1".
MB91520 Series
MN705-00010-1v0-E
1728