Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
36
4.3.4. IFx Arbitration Registers 1, 2 : IFxARB1, IFxARB2
The bit configuration of the IFx arbitration registers 1, 2 is shown.
They are used to write/read message object arbitration data of message RAM. They become invalid in the
test basic mode.
See "4.4 Message Object" for the functions of each bit.
IFx Arbitration Register 2 (upper byte): Address Base + 18
H
& Base + 48
H
(Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MsgVal
Xtd
Dir
ID28 to ID24
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IFx Arbitration Register 2 (lower byte): Address Base + 19
H
& Base + 49
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ID23 to ID16
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IFx Arbitration Register 1 (upper byte): Address Base + 1A
H
& Base + 4A
H
(Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ID15 to ID8
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IFx Arbitration Register 1 (lower byte): Address Base + 1B
H
& Base + 4B
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ID7 to ID0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
See "4.4 Message Object" for explanation of bits.
Note:
If the MsgVal bit of the message object is cleared to "0" while the transmission is in progress, the TxOk bit
of the CAN status register (STATR) will be set to "1" when the transmission has completed. However, the
TxRqst bits of the message object and CAN transmission request register (TREQR) will not be cleared to
"0". So, make sure to clear the TxRqst bits to "0" using the message interface register.
MB91520 Series
MN705-00010-1v0-E
1729