Fujitsu FR81S User Manual
CHAPTER 41: CAN
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
91
5.8. Software Initialization
Software initialization is shown.
Software-controlled initialization is as follows:
The causes of software-controlled initialization are as follows:
⋅
Hardware reset
⋅
Setting of the Init bit of the CAN control register (CTRLR)
⋅
Transition to bus-off state
A hardware reset initializes everything except the message RAM (excluding the MsgVal, NewDat, IntPnd,
and TxRqst bits). After a hardware reset, initialize the message RAM by way of the CPU or reset the
MsgVal bit of the message RAM to "0". If the bit timing register needs to be set, set it before clearing the
Init bit of the CAN control register (CTRLR) to "0".
The Init bit of the CAN control register (CTRLR) is set to "1" on one of the following conditions:
⋅
Write of "1" from the CPU
⋅
Hardware reset
⋅
Bus-off
When the Init bit is set to "1", all message transmission/reception over the CAN bus is suspended and the
CAN_TX pin, which is for CAN bus output, is set to a recessive-level output state (except for CAN_TX test
mode).
When the Init bit is set to "1", the error counter does not change and the registers do not change.
When the Init and CCE bits of the CAN control register (CTRLR) are set to "1", the baud rate control bit
timing register and prescaler extension register can be configured.
Software initialization will terminate when the Init bit is reset to "0". The Init bit can only be reset to "0"
through access from the CPU.
When the generation of 11 consecutive recessive bits (indicating a bus-idling state) are waited after the Init
bit is reset to "0", the CAN controller can be synchronized with the data transfer over the CAN bus. This
can be followed by message transfer.
If the message object Msk, ID, XTD, EoB, and/or RmtEn needs to be changed during ordinary operation,
change it after invalidating the MsgVal bit.
MB91520 Series
MN705-00010-1v0-E
1784