Fujitsu FR81S User Manual
CHAPTER 44: 12-BIT A/D CONVERTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
60
4.3.2. A/D Channel Status Register : ADCH
The bit configuration of the A/D channel status register is shown.
The A/D channel status register (ADCH) shows the analog channel number of conversion target while the
A/D conversion operating.
ADCH0: Address 1462
H
(Access: Byte, Half-word, Word)
ADCH1: Address 15CE
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
CH4
CH3
CH2
CH1
CH0
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0
R0,W0
R0,W0
R,WX
R,WX
R,WX
R,WX
R,WX
[bit7 to bit5] Reserved
These bits must always be written to "0".
[bit4 to bit0] CH4 to CH0 : Analog channel bits
CH4
CH3
CH2
CH1
CH0
Function
ADCH0
ADCH1
0
0
0
0
0
Ch.0
Ch.32
0
0
0
0
1
Ch.1
Ch.33
:
:
:
0
0
1
1
0
Ch.6
Ch.38
0
0
1
1
1
Ch.7
Ch.39
0
1
0
0
0
Ch.8
Ch.40
:
:
:
0
1
1
1
0
Ch.14
Ch.46
0
1
1
1
1
Ch.15
Ch.47
1
0
0
0
0
Ch.16
Setting disable
1
0
0
0
1
Ch.17
:
:
1
1
1
1
0
Ch.30
1
1
1
1
1
Ch.31
These bits can confirm the analog channel number of conversion target while the A/D conversion
operating.
MB91520 Series
MN705-00010-1v0-E
1863