Fujitsu FR81S User Manual
CHAPTER 46: WORKFLASH MEMORY
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WORKFLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
4.3. Flash Interface Control Register : FLIFCTLR (Flash I/F
Control Register)
The bit configuration of the flash interface control register is shown below.
This register controls Flash I/F. This register is shared among program flash and WorkFlash.
FLIFCTLR: Address 2308
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
DFWDSBL
Reserved
ECCDSBL1 ECCDSBL0
Initial value
-
-
-
0
-
0
0
0
Attribute RX,WX
RX,WX
RX,WX
R/W
RX,WX
R/W0
R/W
R/W
[bit7 to bit5] Reserved
These bits are reserved. The read value is undefined. Writing has no effect on the operation.
[bit4] DFWDSBL (Data Fetch Wait cycle Disable) : Data fetch wait cycle disabled
If this bit is set to "1", the wait cycle inserted when setting wait at data fetch is disabled. However, you
cannot disable the wait cycle to guarantee the cycle time.
DFWDSBL
Description
0
Wait cycle enabled (Initial value)
1
Wait cycle disabled
[bit3] Reserved
This bit is reserved. The read value is undefined. Writing has no effect on the operation.
[bit2] Reserved
This bit is reserved. When writing, always write "0" to this bit.
[bit1] ECCDSBL1 (ECC Disable1) : ECC function disable 1
This bit configures enable/disable for the ECC function when write access and data fetch to WorkFlash
memory in the CPU mode.
ECCDSBL1
Description
0
ECC function enabled (Initial value)
1
ECC function disabled
[bit0] ECCDSBL0 (ECC Disable0) : ECC function disable 0
This bit configures enable/disable for the ECC function when write access and data fetch to program flash
memory in the CPU mode.
ECCDSBL0
Description
0
ECC function enabled (Initial value)
1
ECC function disabled
MB91520 Series
MN705-00010-1v0-E
1983