Fujitsu FR81S User Manual
CHAPTER 48: WAVEFORM GENERATOR
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
GATE signal generation when the GATE is active and each OUT is "H"
(TMD8 to TMD0 of the 16-bit dead timer state control (DTSCR0, DTSCR1,
DTSCR2) are "001
DTSCR2) are "001
B
")
Figure 5-2 GATE Signal Generation When the OUT Is "H"
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Count value
Time
Compare register 0
BFFF
H
Compare register 1
7FFF
H
Compare output 0
Compare output 1
GATE0
GATE1
GATE
GATE signal generation from the rising edge of the OUT through the
underflow of the 16-bit dead timer 0, 1, and 2 when the GTEN is active
(TMD8 to TMD0 of the DTSCR0, DTSCR1, and DTSCR2 registers are 010
(TMD8 to TMD0 of the DTSCR0, DTSCR1, and DTSCR2 registers are 010
B
)
Figure 5-3 GATE Signal Generation from the Rising Edge of the OUT through the
16-bit Dead Timer Underflow
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Count value
Time
Compare register 0
BFFF
H
Compare register 1
7FFF
H
Compare output 0
Compare output 1
GATE0
GATE1
GATE
Time of 16-bit
dead timer 0
Time of 16-bit
dead timer 0
MB91520 Series
MN705-00010-1v0-E
2078