Fujitsu FR81S User Manual
CHAPTER 50: RAM DIAGNOSIS FUNCTION
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAM DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
14
4.5. TEST End Address Register XBS RAM : TAEARX
This section explains the bit structure of TEST End Address Register XBS RAM.
TEST end address register (TAEARX) specifies the end address of RAM diagnosis and initialization for
XBS RAM.
•
TAEARX: Address 3018
H
(Access: Byte, Half-word, Word)
15
14
13
12
11
10
9
8
BIT
Reserved
ED14
ED13
ED12
ED11
ED10
ED9
ED8
0
1
1
1
1
1
1
1
Initial values
R0, W0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attributes
7
6
5
4
3
2
1
0
BIT
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
1
1
1
1
1
1
1
1
Initial values
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attributes
[bit15] Reserved
Reserved bit. This bit reads out "0". At writing, write "0".
[bit14 to bit0] ED14 to ED0: RAM diagnosis end address bits
These bits are used to specify the address with which the RAM diagnosis and initialization end for XBS
RAM.
Note:
Setting of a value outside the XBS RAM area and a value that sets TASARX.ST14 to ST0 >
TAEARX.ED14 to ED0 is disabled.
Note:
The above-mentioned address is an offset of the word length.
The absolute address is calculated by adding the base address to the offset address where lower two bits
were added.
(Absolute address) = (0001_0000
H
) + (Offset address set with TAEARX + 2'b00)
MB91520 Series
MN705-00010-1v0-E
2135