Fujitsu FR81S User Manual
CHAPTER 51: TIMING PROTECTION UNIT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : TIMING PROTECTION UNIT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
4.4. TPU Configuration Register : TPUCFG
The bit configuration of TPU configuration register is shown below.
TPUCFG : Address 0908
H
(Access : Byte, Half-word, Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Reserved
DBGE
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
GLBPSE Reserved
GLBPS[5:0]
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R0,W0
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
INTE
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
It is a register that controls the entire TPU.
[bit31 to bit25] (Reserved) : (Reserved bit)
These bits are reserved bits. When writing to those bits, 0 must be set. The readout value is 0.
[bit24] DBGE (Debug Mode Enable) : Debug mode transition
This bit is used to control transition to debug mode.
When debug mode is permitted, all timers stop operating. Each timer restarts operation when coming off
debug mode.
DBGE
Debug Mode
0
All timer operation permission (Normal mode)
1
All timer operation suppression (Debug mode)
MB91520 Series
MN705-00010-1v0-E
2177